A typical reduced instruction set computer (RISC) processor processes instructions in an instruction pipeline. In a typical instruction processing pipeline, instructions are processed sequentially in stages. Typical pipelines contain 3-9 stages. One existing pipeline architecture is a five-stage pipeline that includes an instruction fetch stage, during which the instruction is fetched from memory; an instruction decode stage; an instruction execute stage; a memory access stage, during which memory is accessed for a load/store instruction; and a result write-back stage, during which the result is written to a register file in the processor. Some RISC processors include a co-processor interface through which the RISC processor can intimately issue instructions to another processing element. A processing element that is connected to the RISC processor via the co-processor interface is thus referred to as a co-processor. In existing RISC processors, when an instruction that is being processed is a co-processor instruction, the co-processor instruction is transmitted to the co-processor during the instruction execute stage.
In existing RISC processors, the instruction executed at each stage can raise exceptions or be interrupted. But in order to maintain a manageable order, the exception or interrupt is raised at a fixed stage, say at the memory access stage. This stage will be called the exception raising stage subsequently. When such an event occurs, all instructions before the write-back stage are canceled, and the processor re-starts the execution of the instructions starting with the instruction that was in the memory access stage when the exception/interrupt occurred. In such a scheme, if a co-processor instruction is in the instruction execute stage when an interrupt is received, the co-processor instruction will have been already sent to the co-processor when the interrupt is received. As a result of the interrupt, the co-processor instruction will be cancelled and reissued beginning again at the instruction fetch stage. When the reissued co-processor instruction reaches the instruction execute stage, the co-processor will again be transmitted to the co-processor. Thus, the same co-processor instruction will have been transmitted to the co-processor twice. This condition can cause problems in co-processors in which an issued instruction cannot be cancelled or re-issued. One example of such a co-processor is one that has a consumable buffer storage. With such a co-processor, once a coprocessor instruction is executed, it consumes a certain number of entries of the buffer.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.